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ChipEDA presented a paper Top Down SoC Floor planning with Re-use at IPSOC-2006, Grenoble, FRANCE. We presented an innovative flow for top level SoC routing using ChipMason vRAute™ technology.
 
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White Paper: Top-Down SoC Floor planning with Re-Use 2718
White paper: Integration of a data path generation in an ASIC flow 3166
 
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